Senior Full Chip Physical Design Integration Lead

Job Details

Join Intel as an SOC Physical Design Engineer, where you will play a pivotal role in shaping the future of custom IP and SoC designs. In this position, you will drive the physical design implementation of cutting-edge technologies, transforming RTL to GDS databases ready for manufacturing. Your expertise in physical design flows will directly contribute to optimizing power, frequency, and area metrics, enabling Intel to deliver high-performance products that empower innovation worldwide.

Responsibilities

• Work on SOC floorplan, Pin and macro placement optimizing area and efficiency.
• Perform physical design implementation for custom IP and SoC designs across the entire design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
• Conduct verification and signoff activities such as formal equivalence verification, reliability verification, power integrity analysis, and layout verification using industry-standard EDA tools.
• Drive design optimization across multiple power domains, static and dynamic power integrity analysis, and structural design checking.
• Participate in the development and enhancement of physical design methodologies and flow automation.
• Collaborate with cross-functional teams to ensure designs meet product-level parameters, quality benchmarks, and are ready for manufacturing.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree with 8+ years or master's degree with 6+ years or PhD. with 4+ years in Electrical/ Electronic Engineering, Computer Engineering, Computer Science or a related technical discipline.
• 4+ years of experience with the following technical skills:
  • Proficiency in physical design flows, including synthesis, place and route, clock tree synthesis, and static timing analysis.
  • Expertise in design optimization for physical design, multi-power plane design (MPP/UPF), and RTL to GDS workflows.
  • Hands-on experience with scripting to automate design flows.
  • Knowledge of EDA tools and methodologies for verification, reliability, timing closure, and power integrity analysis.

Preferred Qualifications

• Expertise in Design planning, Hierarchical design, SOC floorplan and optimizations.
• Strong analytical skills with the ability to identify and resolve complex design challenges efficiently.
• Effective communication skills and the ability to work collaboratively within a team-oriented environment.
• Experience developing and improving physical design methodologies and automation tools.
• Familiarity with industry trends and emerging technologies in physical design.

Additional Information

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, Massachusetts, Beaver Brook
• Additional Locations: US, Oregon, Hillsboro
• Work Model: Hybrid
• Salary Range: $164,470.00 - $311,890.00 USD

About the Data Center Group (DCG)

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems.

Benefits

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation.

Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law.